Tuesday, January 29, 2013

TI C6000 SYS/BIOS (1)

  • 66x - shannon with 8 cores
  • DM816x - Netra
  • The key different between Embedded and others: memory design, usage and management. 
  • About 10000 cycles if using "printf" on DSP, about 10 cycles if using internal logprint
  • SYS/BIOS is called BIOS6.x,  it runs on all TI devices, has ARM m3, m4, A8, msp430
  • SYS/BIOS is scalable, real-time kernel, the configuration includes: memory management, real-time analysis, scheduling (thread), synchronization (semaphore...)
  • L1 cache, small and fast in about one cycle, L2 cache with about 2 cycle, share memory between ARM and DSP is about 6-8 cycles, DDR is about 10 cycles
  • Emulator: XDS100 v1, v2, 1mHz with free CCS, Spectral Digital XDS510 10mHz for $1000, Blackhawk XDS 560v2 30-40mHz for $1500.
  • Integer is 32 bits in C6000, short is 16 bits
  • Scheduler is the most important part of BIOS
  • Pre-emptive: highest priority always wins
  • the word "thread": functions running with priorities within a specific context (stack)
  • Switch tasks need 500 cycles, swith SWI need 200 cycles

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