Friday, February 01, 2013

TMS320C674x Architecture

Level 1 Data (L1D) cache, small and fast inside 1 cycle
Level 1 Program (L1P) cache
L2 cache is about 2 cycle
Through SCR (switched central resource) will slow down
L3 is shared memory between ARM and DSP, about 6-8 cycles
DDR2 is about 10 cycles

No comments:

Post a Comment